The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of stably providing an internal voltage.
Generally, semiconductor memory devices store a plurality of data and provide the stored data when the data are required to be read out. The basic operation of the semiconductor memory device is a write operation to store data in determined cells and a read operation to output the stored data. It is necessary to have different levels of an internal voltage in order to perform the read and write operations effectively. In order to perform the read and write operations of the semiconductor memory device, there are needed a core voltage used for a data storage area in which a plurality of data are stored and a peripheral voltage used for a peripheral area in which data input and output operations are carried out. DRAM of the semiconductor memory devices, which has been most widely used, comprises a unit cell for storing one data with one MOS transistor and one capacitor. In order to turn on the MOS transistor of the unit cell, the semiconductor memory device uses a high voltage which is higher than the core voltage by a predetermined voltage level and a bulk voltage which is lower than a ground voltage by a predetermined voltage level.
The semiconductor memory device produces various internal voltages, for example, the core voltage, the high voltage, the bulk voltage and the like, to access the data based on a power supply voltage and a ground voltage supplied from an external circuit. To produce these internal voltages, the semiconductor memory device includes an internal voltage generating circuit and a detection circuit to decide whether a voltage level from the internal voltage generating circuit is kept in a predetermined voltage level.
On the other hand, after the semiconductor memory devices are manufactured, they are checked out through the various tests to decide whether the manufactured memory devices carry out a stable operation. At this time, one of the various tests is a burn-in mode test. The burn-in mode test is to detect a potentially erroneous unit cell at its early stage by applying a high voltage, which is higher than a voltage of the normal operation, to the semiconductor memory device and by making this semiconductor memory device operate at a high temperature. In the process where the semiconductor memory devices are manufactured, if there are minute defects in a part of a plurality of unit cells, they will be in a latent failure which does not appear at the moment. To detect the latent failure of the unit cell at its early stage, the burn-in mode test to operate the memory device in the burn-in environment, which is more severe than the normal environment, is carried out.
Accordingly, the semiconductor memory device should generate a different internal voltage level, which differs from a voltage level required to access the data in the normal mode, at the time of the burn-in mode test. Therefore, the semiconductor memory devices have to additionally include a burn-in mode internal voltage generating circuit for the burn-in mode test, independent of the normal mode internal voltage generating circuit. An area of the circuit, which is additionally equipped for the burn-in test, is critical to reduce the total area of the semiconductor memory device.